Synopsys -- How the Business Works

Synopsys is the global leader in Electronic Design Automation (EDA), providing the software, IP, and hardware that chip designers use to create and verify semiconductor devices. Together with Cadence, Synopsys forms a duopoly controlling ~65% of the EDA market -- a textbook oligopoly where switching costs span years, tools are foundry-certified at each process node, and no viable open-source alternative exists for advanced nodes. Following the $35B acquisition of Ansys (closed July 2025), Synopsys has repositioned as a silicon-to-systems engineering platform, expanding its TAM from ~$15B (EDA+IP) to ~$31B (adding simulation/analysis). 84% of revenue is recurring via subscriptions, with $11.3B in backlog providing ~1.2x forward revenue visibility.

FY26Q1 Revenue

$2.41B

+65.5% YoY (incl. Ansys)

Recurring Revenue

84%

Subscription/ratable model

EDA TAM (post-Ansys)

~$31B

Doubled from ~$15B pre-Ansys

Backlog

$11.3B

~1.2x forward revenue visibility

Revenue by segment -- Design Automation is the core, Ansys is the growth lever

Revenue by Segment -- FY26Q1 ($2.41B Total)

Design Automation 83% -- $2,002M (incl. Ansys)

Design IP 17% -- $407M

Design Auto FY24Q2

$1,055M

Pre-Ansys baseline

Design Auto FY25Q4

$1,848M

+65.2% YoY (first full Ansys Q)

Design Auto FY26Q1

$2,002M

+96.2% YoY

The EDA duopoly -- the deepest moat in software

Synopsys and Cadence form a textbook duopoly in EDA, with combined ~65% market share in a market where:

Switching costs span years and involve re-qualifying entire chip design flows across hundreds of engineers
Tools are foundry-certified at each process node (design-technology co-optimization with TSMC, Samsung, Intel)
No viable open-source alternative exists for advanced nodes -- chip design at 2nm and below is impossible without commercial EDA
Customer R&D budgets are growing (semiconductor R&D spending rising from ~6% to ~9% of sales, per CEO Ghazi)
Virtually 100% of advanced-node tape-outs (2nm and below) use Synopsys tools

This is not a market that can be disrupted by a startup. The certification requirements, decades of accumulated IP, and deep integration with foundry processes create barriers that are effectively permanent. The duopoly structure ensures rational pricing, with both Synopsys and Cadence able to raise prices in line with the growing complexity of chip design.

Ansys acquisition -- from silicon to systems

The $35B acquisition of Ansys (closed July 2025) is the most transformative deal in Synopsys history, repositioning the company from an EDA vendor to a silicon-to-systems engineering platform:

Ansys contributing ~$2.9B revenue in FY2026 (double-digit growth)
First joint solutions expected 1H 2026 (multiphysics + EDA for 3DIC, advanced packaging)
Revenue synergy target: $400M run rate by year 4
Cost synergy target: $400M run rate by year 3 (10% workforce reduction largely complete)
Expands TAM from ~$15B (EDA+IP) to ~$31B (adding simulation/analysis)
Cross-selling underway with sales teams already trained on combined portfolio
NVIDIA partnership supports Ansys acceleration via GPU computing + Omniverse digital twins

The strategic logic is compelling: as chips become 3D stacked systems (chiplets, advanced packaging), designers need both electronic and physical simulation in a single workflow. Ansys brings multiphysics (thermal, structural, electromagnetic) to complement Synopsys EDA, creating a platform that no competitor can replicate.

Design IP -- interface IP leader in a transitional year

Synopsys is the leader in high-speed interface IP, providing the pre-designed building blocks that chip designers embed into their chips:

Product portfolio: PCIe, SerDes, UCIe, HBM, LPDDR, Ultra Accelerator Link (UAL), Ultra Ethernet IP
40+ PCIe design wins in FY26Q1 alone; first-to-market PCIe 8.0 demonstration
Industry-first UAL and Ultra Ethernet IP for AI cluster interconnects
Standards evolution pace doubled from 3-4 year to ~1.5-2 year cycles, increasing IP refresh demand
Divesting ARC processor IP to GlobalFoundries to sharpen focus on interconnect/foundation IP

FY2026 is a transitional year for the IP business. Revenue declined from $517.8M (FY24Q4) to $407.0M (FY26Q1), with margins compressing from ~38% to 16.2% as R&D investment in HPC titles continued while some deliveries were delayed. Management has made leadership changes and expects recovery in 2H FY2026, with long-term mid-teens growth reaffirmed.

Revenue model -- subscription-first with expanding platform

Synopsys operates a highly recurring revenue model that provides exceptional visibility:

84% recurring revenue via multi-year subscription agreements (typically 3+ years)
$11.3B backlog providing ~1.2x forward revenue coverage
Ratable recognition -- revenue is recognized evenly over the contract term, smoothing quarterly results
Hardware-assisted verification (ZeBu/HAPS) adds a lumpy but high-margin complement to the subscription base -- had record years as AI chip verification complexity surges
IP licensing generates royalties on shipped chips plus upfront licensing fees
Post-Ansys: Simulation/analysis adds another layer of recurring software revenue with natural cross-sell into the existing EDA customer base

The combination of subscription pricing, multi-year contracts, deep customer lock-in, and an expanding platform (EDA + IP + Ansys simulation) creates one of the most durable recurring revenue streams in enterprise software.

Data sourced from Daloopa and earnings transcripts.